The present invention relates generally to the field of memory modules and, in particular, to providing super voltages to memory modules.
Voltages are often applied to a memory module, such as a single in-line memory module, a dual in-line memory module, or the like, to place a memory device of the module, such as dynamic random access memories (DRAMs), static random access memories (SRAMs), or the like, into a test mode. Moreover, such voltages are often used to blow one or more anti-fuses, for example, while a memory device is in a test mode. Blowing of one or more anti-fuses is commonly employed to provide a circuit path that bypasses a defective primary circuit element of a memory device, for example, as identified in a test mode, to replace the defective primary circuit element with a redundant circuit element. These voltages are typically greater than the normal operating voltages supplied to the memory module and are usually referred to as super voltages. Super voltages are applied the memory module when the memory module is not connected for use, e.g., not connected to a motherboard. For example, super voltages are often applied during a checkout phase of a manufacturing process for memory modules.
One method for supplying super voltages to several memory devices on a memory module involves using an address pin(s) on the memory module that is connected to an address pin on each of the memory devices. The address pins typically experience two voltage levels during operation, e.g., approximately zero and approximately two to five volts. These voltage levels are transmitted to the address pin on each memory device. When the memory module is not connected for use, the super voltage can be selectively applied to the address pin on the memory module, which transmits the super voltage to the address pin on each memory device to place the respective memory devices into a test mode and/or to blow one or more anti-fuses. A chip-select signal can be used to select one of the memory devices to be tested.
One problem with using an address pin on a memory module to supply super voltages to a memory device is that voltage threshold circuitry usually needs to be added to the address pin on the memory. The added circuitry increases the complexity and thus the cost of the memory. Another problem is that noise on the address pin of the memory module during operation may increase the risk of accidentally placing the memory devices into the test mode, thus removing the memory devices from normal operation.
For the reasons stated above, and for other reasons stated below which will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art for memory modules that provide alternatives to using address pins on the memory modules to trigger test modes of memory devices on the memory modules.
The above-mentioned problems with using address pins on memory modules to supply super voltages to memory devices on the memory modules and other problems are addressed by embodiments of the present invention and will be understood by reading and studying the following specification. Embodiments of the present invention provide memory modules that provide alternatives to using address pins on memory modules to supply super voltages to memory devices on the memory modules. These embodiments mitigate the problems associated with using address pins on memory modules to supply super voltages to memory devices on the memory modules.
More particularly, in one embodiment, a memory module is provided. The memory module has a memory device that has a test pin. A pin of the memory module is connected to the test pin. The pin of the memory module connects the test pin to one of ground, a power source, or an open circuit when the memory module is connected for operation. The pin of the memory module selectively supplies a super voltage to the test pin when the memory module is not connected for operation.
In another embodiment, a memory module is provided that has a memory device having a test pin, a resistor-capacitor circuit connected to the test pin, a buffer connected to the resistor-capacitor circuit, and a diode connected to the test pin and to the resistor-capacitor circuit. A pin of the memory module is connected to the diode. The pin of the memory module connects the test pin to one of ground, a power source, or an open circuit when the memory module is connected for operation. The buffer selectively transmits first and second signals to the test pin via the resistor-capacitor circuit when the memory module is connected for operation. When the memory module is not connected for operation, the pin of the memory module selectively supplies a super voltage to the test pin via the diode.
Other embodiments are described and claimed.